Chip design and verification engineers typically write up to 10 lines of test bench code for each row of RTL code implemented on silicon. Verification tasks can take up to 50% or more of the design cycle. Despite this hard work, nearly 60% of the chips still have functional flaws and need to be reworked. Because HDL simulation is not enough to detect system-level errors, chip designers are using FPGAs to accelerate algorithm creation and prototyping. Using FPGAs to process large test data sets allows engineers to quickly evaluate algorithms and architecture and quickly make trade-offs. Engineers can also test designs in real-world environments to avoid the time spent using HDL simulators. System-level design and verification tools such as MATLAB and Simulink help engineers achieve these benefits by quickly building algorithm prototypes on FPGAs. This article describes the best way to create an FPGA prototype using MATLAB and Simulink. These best practices include: analyzing the effects of fixed-point quantization and optimizing word lengths at the beginning of the design process to produce smaller, more efficient implementations; using automated HDL code generation to generate FPGA prototypes faster; reusing HDL co-simulation The system-level test platform uses the system-level indicator to analyze the HDL implementation; it accelerates verification through FPGA-in-the-loop simulation (Figure 1). Why build a prototype on an FPGA? Building algorithm prototypes on FPGAs can increase the confidence of engineers to believe that their algorithms perform as expected in real-world environments. In addition to running test vectors and simulations at high speeds, engineers can take advantage of FPGA prototyping software capabilities and related system-level functions such as RF and analog subsystems. In addition, because FPGA prototypes run faster, large data sets can be used, exposing defects that are not found in the simulation model. Model-based design with HDL code generation enables engineers to efficiently build FPGA prototypes, as shown in Figure 2. This picture shows us the reality that engineers often shorten the detailed design phase and try to meet the development cycle requirements by starting the hardware development phase as soon as possible. In reality, when an engineer finds that the fixed-point algorithm does not meet the system requirements, he has to re-examine the detailed design phase during the HDL creation phase. Such overlapping work will lengthen the HDL creation phase (as indicated by the purple strip) and may lead to various design issues (such as glue logic or design patches). Because the automated HDL code generation process is faster than manual coding, engineers can devote the time saved to the detailed design phase to produce better quality fixed-point algorithms. This approach enables engineers to generate better quality FPGA prototypes faster than manual workflows.
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