The use of FPGA is more extensive than we usually imagine, because there are more types of integrated modules, not just the original simple logic unit (LE). Early FPGAs were relatively simple. All functional units were constructed from pins, internal buffers, LE, and RAM. LE was composed of LUTs (look-up tables) and D flip-flops, and RAM was often very small. The current FPGA not only includes the previous LE, the RAM is also larger, faster and more flexible, the management IOB is also more complex, and supports more IO types, and it also integrates some special functional units, including: DSP: In fact, it is a multiplier and adder. Multiple multipliers and adders can be integrated inside the FPGA, while the general DSP chip often has only one per core. In other words, FPGA can more easily implement multiple DSP core functions. In some occasions that require a large number of multiplication and addition calculations, often the speed of multiple multipliers and adders working in parallel can far exceed a high speed multiplier and adder. SERDES: High-speed serial interface. In the future, there will be more and more high-speed serial interfaces such as PCI-E, XAUI, HT, and S-ATA. With the SERDES module, FPGA can easily integrate these high-speed serial interfaces, without the need to purchase special interface chips. CPU core: There are two types, soft core and hard core. Soft core is a CPU module written with logic code, which can be implemented in any FPGA with sufficient resources and is very flexible to use. Moreover, multiple soft cores can be integrated in a large-capacity FPGA to realize multi-core parallel processing. The hard core is a CPU core made inside a specific FPGA. The advantages are fast speed and good performance, but the disadvantage is that it is not flexible enough. However, FPGAs still have shortcomings. For some high-frequency applications, FPGAs are powerless. Although FPGA can support 500MHz theoretically, in actual design, it is often difficult to achieve operating frequencies above 200MHz. One of the key points of FPGA design: clock tree For FPGAs, asynchronous design should be avoided as much as possible, and synchronous design should be adopted as much as possible. The first key to the synchronization design, and the key in the key, is the clock tree. A bad clock tree is an irreparable disaster for FPGA design. It is a building without a good foundation, and its collapse is inevitable. Specific design rules: 1) Use a single clock as much as possible; 2) If there are multiple clock domains, they must be carefully divided and be careful; 3) Signals across clock domains must be synchronized. For control signals, double sampling can be used; for data signals, asynchronous fifo can be used. It should be noted that asynchronous fifo is not a panacea, and an asynchronous fifo can only solve the frequency difference problem within a certain range. 4) Use the PLL and DLL inside the FPGA as much as possible, which will bring a lot of benefits to your design. 5) For special IO interfaces, you need to carefully calculate Tsu, Tco, and Th, and use PLL, DLL, DDIO, pin-set delay and other tools to achieve. It is often impossible to simply constrain the pins of Tsu, Tco, and Th. It may not be very accurate. The clock tree here actually refers to the clock scheme, mainly the planning of the clock domain and PLL, etc. Generally, the detailed calculation of the routing delay is not involved (generally, the global clock network and the local clock network are used, and the delay is fixed) , Which is different from the clock tree in ASIC. For ASIC, it is necessary to carefully analyze and calculate the design, wiring, and delay calculation of the clock network. FPGA design point two: FSM FSM: Finite state machine. This can be said to be the basis of logic design. Almost a slightly larger logic design, almost all FSM can be seen. FSM is divided into moore type and merly type. The state transition of moore type has nothing to do with variables, while the merly type is related. In actual use, most of them use merly type. FSM is usually written in two ways: single-process and dual-process. Beginners often like single-process writing, the format is as follows: Simply put, single-process FSM puts all synchronous and asynchronous processing into one always. advantage: 1) It seems relatively simple and clear, and it is not necessary to write all the processing of each signal and status signal in each case branch or if branch. You can also simply add some counters to it for counting processing. 2) All output signals have been latched by D flip-flops. Disadvantages: 1) The optimization effect is not good. Because synchronization and asynchronous are put together, the compiler generally optimizes the asynchronous logic best. The result of the single-process FSM mixing synchronization and asynchrony is the poor optimization effect of the compiler, which often leads to slow logic speed and high resource consumption. 2) In some cases, faster signal output is needed, and it is not necessary to pass through the D flip-flop latch. At this time, the processing of single-process FSM is more troublesome. Dual-process FSM, the format is as follows: As you can see from the above, synchronous processing and asynchronous processing are put into 2 always. Among them, two FSM state variables are also used for control. I won't say much about the principle of dual-process FSM here, as it is introduced in many logic design books. It is too laborious to describe here. advantage: 1) The optimization effect of the compiler is obvious, and the ideal speed and resource occupancy rate can be obtained. 2) All output signals (except FSM_status_current) are combined output, which is faster than single-process FSM. Disadvantages: 1) All output signals (except FSM_status_current) are output in combination, and in some cases, additional code is required for latching. 2) In asynchronous processing always, all if and case branches must assign all output signals, and the output signal in the FSM cannot be returned and assigned to other signals in the FSM, otherwise there will be a latch. Latches can cause the following problems: 1) The result of functional simulation does not match the post-simulation; 2) Untestable logic appears; 3) The logic work is unstable, especially the latch part is extremely sensitive to glitches; 4) Under certain and special circumstances, if positive feedback occurs, it may lead to disastrous consequences. This is not a threat or a joke. I saw a guy who loaded the logic he made and the entire FPGA was blown up. Later, it was suspected that positive feedback might cause high-frequency oscillations, and finally caused the chip to overheat and blow up (this FPGA chip does not have a heat sink). The third point of FPGA design: latch First answer: 1) StateCAD has not been used before, but I feel it is not very convenient to use this stuff to build a large system. Maybe it's better to use systemC or system Verilog. 2) The name of synchronous and asynchronous is the customary name of my company, which is not quite right, but I am used to it, haha. Let's talk about latch this time. The hazards of latches have already been said, so I won't say more here, but the key is to talk about how to avoid them. 1) In the combinatorial logic process, the if statement must have an else! and all signals must be assigned in all branches of the if. In addition, it should be noted that the latch will also be generated below. That is to say, in the combinatorial logic process, it is not possible to assign itself to itself or indirectly appear to be assigned to itself. But if it is a sequential logic process, this problem does not exist. 2) The default of the case statement must not be less! The reason is the same as the if statement, so I won't say more here. What needs to be reminded is that in the sequential logic process, the default statement must also be added, which is a good habit. 3) Sensitive variables of the combinatorial logic process cannot be less or more. This problem is not too big, you can use * directly in the verilog2001 grammar. By the way, if the latch has disadvantages, it must be advantageous. In the LE of the FPGA, there is always a latch and a D flip-flop, and there is also a latch in the IOE (IOB) that supports DDR to implement DDIO. However, in our usual design, we should keep the latch as far away as possible. . FPGA design point four: logic simulation Simulation is an essential step in FPGA design. Without simulation, there is nothing. Simulation is a monotonous and tedious task, and it is easy for people to give up or cut corners. Be sure to hold on at this time! Simulation is divided into unit simulation, integrated simulation, and system simulation. Unit simulation: simulation for each minimum basic module. Unit simulation requires code line coverage, conditional branch coverage, and expression coverage to reach 100%! These three coverage rates can be viewed through MODELSIM, but they need to be set in the Compile option when compiling the module. Integrated simulation: combine multiple large modules together for simulation. The coverage rate is required to be as high as possible. System simulation: Simulate the entire hardware system together. At this time, the entire simulation platform includes simulation models of logic peripheral chip interfaces, as well as BFM, Testbench, and so on. System simulation needs to carefully design simulation test cases and simulation test platforms according to the function and performance requirements of the simulated logic. System simulation is a large branch of logic design and a subject that requires specialized learning. Outdoor low power LED lamps,Aluminum Alloy LED lamps,LED Flood light series Kindwin Technology (H.K.) Limited , https://www.ktlleds.com